1. Field of the Invention
The invention relates to computer clocking systems, and more particularly, to methods of starting up computer clocking systems that use phase-locked loops to generate local system clock signals from master clock signals. The invention further relates to devices for realizing such methods.
2. Description of the Related Art
In efforts to realize greater computing power, microprocessor developers have continuously pushed the clock speeds ever higher. As few as ten years ago, microprocessor clock frequencies of 16 MHz were rare. Today, one sees microprocessors running at frequencies of 50 MHz and even higher.
With these higher clock frequencies have come concurrent problems. Distribution of a 50 MHz clock to the various components of a digital computer system can present difficulties associated with electromagnetic interference (EMI), clock skew, and reflections of the higher harmonics of the system clock signal. Transmission of high frequency clock signals over connectors to companion boards exacerbates these problems.
Developers have sought creative solutions to these problems. One approach has been to rely on a lower frequency system clock, and then generate, on the microprocessor or peripheral chip itself, a higher frequency clock signal from that lower frequency system clock. A number of current microprocessors and peripheral chips implement such a technique, for example, the 80486DX2 by Intel Corporation. This technique has the advantage of increasing a chip's internal processing rate without requiring a corresponding increase in system clock frequency, thus avoiding the problems associated with those higher clock rates.
To generate these higher frequency internal clock signals, these chips typically use a phase-locked loop (PLL) configured as a frequency multiplier. A block diagram of such a frequency multiplier circuit is shown in FIG. 1. As is shown, a phase detector (or phase comparator) drives, through a filter, a voltage controlled oscillator (VCO). The output of that VCO, which becomes the output signal, is then divided by the desired multiplication factor, and then the phase detector compares that divided reference signal with the input signal. This feedback arrangement compensates for shifts in the phase and frequency of the input signal by a level shift to the VCO, and the output signal is thus synchronized to the input signal. Examples of PLLs that can be configured as frequency multipliers include the CD4046A by RCA Corporation and the 74LS297.
The phase detector has two main purposes. First, it forces the VCO to shift frequencies when the reference signal and the input signal are of different frequencies. Second, it forces slight corrections to the VCO output when the reference and input signals are of the same frequency but are slightly out of phase. Both of these functions are accomplished by adjusting the frequency of the VCO; it is simply a difference of the magnitude of the adjustment.
A lock-in detection circuit can also use the output of the phase detector to determine when the PLL is locked onto the input signal. Phase-locked loops and lock-in detectors are well known to those skilled in the art of electronics design. Further information can be found in "The RCA COS/MOS Phase-Locked-Loop: A Versatile Building Block for Micro-Power Digital and Analog Applications." in: RCA COS/MOS Integrated Circuits (1978), pp. 598-601, which is incorporated herein by reference.
A PLL, however, has certain characteristics that can cause their own problems. Before an input signal is applied to a PLL, its VCO runs unrestricted at a frequency known as the free running frequency. The free running frequency is typically much higher than the frequency at which the PLL will ultimately lock. In fact, the signal initially output by the unlocked PLL may be higher than what would be allowed by the system in which the PLL is to be used. Thus, at system startup, any circuit using a PLL must take this free running frequency into account.
Further, when an input signal is first provided to a PLL, the reference signal does not instantaneously lock onto that input signal. A delay known as the capture time must pass before the PLL locks. The exact length of this delay is variable, but typically the output signal will become stable after a certain maximum delay.
Microprocessors and their support chips typically have minimum and maximum allowable clock input frequencies. Driving these chips at clock frequencies outside their specifications is not only logically unpredictable, but can also physically damage these devices. Thus, if a microprocessor is rated for a 50 MHz clock rate, driving that microprocessor at 100 MHz, for example, could destroy the microprocessor. In integrated circuits using CMOS and related technology, power consumption, and thus thermal heating, is proportionally related to the clock frequency. Thermal breakdown can thus be a failure mode for driving a chip beyond its rated clock frequency.
Another problem with PLLs is that as they attempt to lock onto the input signal, their output signals can change rapidly. Many microprocessors and peripheral devices cannot accommodate such rapid fluctuations of input clock frequencies. For example, using the Intel 80486-50, the maximum allowable fluctuation in clock period for adjacent clock cycles is 0.1%, or 20 picoseconds.
So, if a PLL is used to generate a system clock, it would be desirable to prevent such a circuit from outputting a clock signal of a frequency that is outside the rated parameters of the integrated circuits that will be driven by this generated clock. Further, it would be desirable for such a circuit to avoid outputting a clock signal whose frequency is rapidly changing. Such techniques would be particularly important when the system is first started up.